As described in the above-referenced '836 application, electrical power for an integrated circuit (IC) is typically supplied by one or more direct current power sources, such as a buck-mode, pulse width modulation (PWM) based, DC-DC converter of the type diagrammatically shown in FIG. 1. As shown therein, a PWM control circuit 10 supplies a PWM signal to a switching circuit driver 20, that controls the turn-on and turn-off of a pair of electronic power switching devices, to which a powered load is coupled. In the illustrated DC-DC converter, the electronic power switching devices are depicted as an upper (or high side) power NMOSFET (or NFET) device 30, and a lower (or low side) power NFET device 40, having their drain-source current flow paths connected in series between a pair of power supply rails (e.g., VIN and ground (GND)).
The upper NFET device 30 is turned on and off by an upper gate switching signal UGATE applied to its gate from driver 20, while the lower NFET device 40 is turned on and off by a lower gate switching signal LGATE supplied from driver 20. A common node 35 between the two NFETs is coupled through an inductor 50 to a load reservoir capacitor 60 that is coupled to a reference voltage terminal (GND). The connection 55 between inductor 50 and capacitor 60 serves as an output node 55 from which a desired (regulated) DC output voltage Vout is applied to a LOAD 65 (coupled to GND).
The output node connection 55 is also fed back to error amplifier circuitry 12 within the PWM controller 10. The error amplifier circuitry is used to regulate the converter's output DC voltage relative to a reference voltage supply. In addition, the common node 35 between the controllably switched NFETs is coupled (as by way of a sense feedback resistor 45) to current-sensing circuitry 15 within the controller 10. The controller adjusts duty ratio of the PWM signal, as necessary, to maintain the converter's DC output within a prescribed set of parameters.
The controller 10 of FIG. 1 can be implemented with either analog or digital circuits. The digital implementation is desirable for all the reasons that have historically favored digital signal processing techniques, but there is a penalty. A digital controller produces a quantized PWM pulse width, i.e., the PWM pulse width has an irreducible temporal granularity associated with the finite bit length of the digital implementation. The digital PWM granularity imposes performance limitations on the DC-DC regulator in a manner similar to noise in the analog PWM pulse generation. Electronic circuits and systems powered by PWM-based DC-DC converters of the type shown in FIG. 1 require precise DC-DC regulation, and the required precision of regulation is tightening with each successive generation of circuits and systems. Consequently, it is desirable to have high digital resolution (small temporal granularity) of the PWM pulse by which the duty-cycle of the PWM signal may be (digitally) adjusted to translate (e.g., step down) the supply voltage (e.g., 12 VDC) to a prescribed regulated fraction thereof (e.g., one-eighth or a 1.5 VDC regulated output voltage).
Ostensibly, this may be accomplished by controlling the operation of the digital PWM pulse generator with a clocking frequency that is a multiple of the switching frequency to which the PWM generator is referenced. As a non-limiting example, consider the case of a switching frequency of 1 MHz, a digital clock frequency of 100 MHz, and a nominal PWM duty-cycle of 10%. The digital clock cycle resolution limits the actual duty-cycle to P/100, where P is an integer number of clock cycles that make up a single PWM pulse, and 100 is the number of clock cycles in a switching period. This means that the duty-cycle resolution in the vicinity of the nominal value PWM duty-cycle of 10% is +/−1%, namely 9% or 11%. In either case the actual digital granularity is very coarse, +/−10% when considered as a fraction of the nominal 10% duty-cycle.
One way to improve upon this relatively coarse digital resolution is to increase the ratio of the reference clock signal to the PWM switching frequency—either by decreasing the switching frequency and/or increasing the frequency of the reference clock signal. In the above example, a finer granularity/resolution on the order of 0.1% of duty-cycle, or 1% of the nominal 10% duty-cycle, could be obtained by decreasing the PWM switching frequency to 100 KHz (while maintaining the reference clock frequency at 100 MHz), or increasing the reference clock frequency to 1 GHz (while maintaining the PWM switching frequency at 1 MHz). Unfortunately, both choices obviously result in impractical solutions in light of other system requirements and limitations.
A proposed analog technique to address this problem is to employ a tapped delay line-based digital PWM pulse generator of the type shown in FIG. 2, an associated timing diagram for which is illustrated in FIG. 3. In accordance with this approach, an Integer PWM Pulse that encompasses a prescribed number P of clock cycles of a reference clock signal CLOCK is applied to a multistage delay line 200 that contains a plurality of cascaded delay stages 200-1, 200-2, . . . , 200-N (each of which may be comprised of a pair of (MOSFET) inverter stages). The delay time through each delay stage corresponds to the minimum time resolution or granularity by which the PWM pulse may be adjusted.
The output of each delay stage is coupled to a respective input of a N+1:1 signal selector 210, which has its output coupled to one input of an OR gate 220. A second input of the OR gate 220 is coupled to receive the Integer PWM Pulse. As a result, OR gate 220 logically OR's the Integer PWM Pulse with the output of whichever delay stage 200-j is selected in accordance with a fractional delay select signal coupled to the select input 212 of signal selector 210.
Depending upon the delay Di imparted by each delay stage, and depending upon which jth one of its inputs is selected, signal selector 210 will produce a version of the Integer PWM Pulse as a Delayed Integer PWM Pulse delayed by j×Di. Logically ORing the Integer PWM Pulse and the Delayed Integer PWM Pulse produces a Non-Integer PWM Pulse having a front edge (e.g., rising edge) 301 that is coincident with the front edge (e.g., rising edge) 311 of the Integer PWM Pulse and a termination (e.g., falling edge) 302 that is coincident with the termination (e.g., falling edge) 312 of the Delayed Integer PWM Pulse.
Although the fractional delay scheme of FIG. 2 provides a potentially effective solution to the PWM digital resolution problem, it is limited by a number of practical considerations, such as differences among fabrication runs of its integrated circuit manufacturing process, and operational variations, such as changes in temperature and/or supply voltage. In accordance with the invention disclosed in the above-referenced '836 application, such shortcomings can be substantially reduced by a PLL-configured, or ‘pseudo’ PLL-configured, fractional clock pulse generator, whose operational (delay stage) parameters are adjusted as necessary to maintain a desired fractional precision of the duty-cycle of a generated PWM clock pulse signal.
In accordance with a first, closed-loop, PLL approach, shown diagrammatically in FIG. 4, the tapped delay line-based digital PWM pulse generator of FIG. 2 is augmented to include a compensating phase locked-loop, that is formed around an auxiliary tapped delay line 400, which implements the voltage controlled oscillator (VCO) component of a PLL. One or more parameters (e.g., layout geometries) of the respective delay line stages of the auxiliary delay line 400 have a predetermined relationship with respect to those of the PWM delay line 200, based upon the desired operating characteristics of the PWM pulse generator, as well as desired performance of the PLL.
To facilitate digital processing applications, it is preferred, but not required, that the granularity of the duty-cycle of the PWM pulse be adjustable in fractions that are an integer power of 2 (e.g., by one-sixteenth of a clock cycle). On the other hand, the nominal inverting delay of the PLL should be a prime number fraction (e.g., one-seventeenth of a clock cycle), to prevent the generation of harmonics in the PLL. To accommodate both of these objectives, properties (e.g. geometries) of the delay stages of the auxiliary delay line 400 of the PLL are appropriately correlated with those of PWM delay line 200, so that the same operational adjustment parameter (e.g., bias voltage) can be used to produce slightly different precisely correlated delays in the respective stages of the two delay lines.
The auxiliary tapped delay line 400 includes a plurality of cascaded delay line stages 400-1, 400-2 . . . , 400-K, the number and configuration of each of which correspond to those of tapped delay line 200, so that the auxiliary tapped delay line 400 may be considered to be an effective ‘copy’ of the tapped delay line 200 of FIG. 2. To implement a VCO, the output of a first inverter INVK-1 of the Kth delay stage 400-K of delay line 400 is fed back to the input of the first inverter INV1-1 of its first delay stage 400-1, so as to form a ‘ring’-configured, delay stage-based oscillator, which produces an output clock frequency which the PLL can lock to the clock signal CLOCK. The output of a second inverter INVK-2 of the Kth delay stage 400-K is coupled to a first input 431 of a phase detector 430, which has a second input 432 coupled to receive the clock signal CLOCK. The CLOCK period is approximately equal to the nominal delay of the full PLL delay line (400); thus under nominal conditions the PLL delay line will impose a one clock cycle delay on the CLOCK signal.
As in a conventional PLL, the output 433 of phase detector 430 provides a phase error signal that is used to adjust the operation of the tapped delay line-implemented VCO 400. As a non-limiting example, this phase error adjustment path is shown as comprising a bias voltage control unit 440, which controls the DC bias voltage applied to each of the delay stages of the delay line VCO 400. The output of the bias voltage control unit 440 is also used to control the DC bias voltage applied to the delay stages of tapped delay line 200 within PWM pulse generator 420.
Since the respective delays imparted by the delay stages of the auxiliary PLL delay line 400 are appropriately correlated with those of the delay stages of the PWM tapped delay line 200, then whatever adjustment is carried out in the PLL 410 to lock its tapped delay line (VCO) 400 to the reference CLOCK causes an associated adjustment of the delays of the delay line stages of the PWM pulse generator 420, and thereby provides a high precision fractional adjustment of the duty-cycle of the Integer PWM Pulse that is effectively independent of processing variations and operational parameters such as temperature and supply voltage.
According to a second ‘pseudo PLL’ open loop approach, shown diagrammatically in FIG. 5, the Integer PWM Pulse is coupled via input terminal 501 to a first inverter INV1-1 of a first delay stage 500-1 of a multistage tapped delay line 500. Being open loop, no delay stage of the delay line 500 has its output fed back to the delay line's input stage 500-1. The number of stages N of delay line 500 determines the resolution, or granularity, to which the system clock signal CLOCK may be divided, and nominally encompasses one cycle of the system clock signal. The Integer PWM Pulse is also input to a register delay 550 that imparts a single (PWM) system clock cycle delay to the Integer PWM Pulse producing the Unity Delayed Integer PWM Pulse. The Unity Delayed Integer PWM Pulse is applied to a first input 511 of a phase detector 510. The output of a second inverter INVN-2 of the Nth delay stage 500-N is coupled to a second input 512 of the phase detector 510.
In addition to being coupled in cascade between the Integer PWM Pulse input terminal 501 and the phase detector 510, the outputs of the N delay stages 500 are coupled to respective inputs of a N:1 signal selector 530, whose output is coupled to one input of an OR gate 540. A second input of the OR gate 540 is coupled to receive the Integer PWM Pulse. As in the embodiment of FIG. 4, OR gate 540 will logically OR the Integer PWM Pulse applied to input terminal 501 with the output of whichever delay stage 500-j is selected in accordance with a select signal coupled to the select input 532 of signal selector 530. Thus, the output of the OR gate 540 produces the PWM pulse whose leading edge is coincident with that of the Integer PWM Pulse and whose trailing edge is coincident with the trailing edge of the output of the selected delay stage.
Like the closed loop PLL embodiment of FIG. 4, the output 513 of the phase detector 510 provides a phase error signal that adjusts operational parameters of the delay stages of the tapped delay line 500. In particular, the output 513 of the phase detector 510 is coupled to a bias voltage control unit 520, which controls the bias voltage applied to each of the delay stages of the delay line 500. In the open loop ‘pseudo PLL’ embodiment of FIG. 5, however, phase detector 510 is referenced to the Unity Delayed Integer PWM Pulse, rather than the high frequency system clock CLOCK. The duration of the PWM output pulse is thereby determined by the system clock delay granularity imparted by a respective one of the delay line stages 500-i, and from which delay line stage output the PWM pulse signal is derived.
The phase detector 510 compares the Integer PWM Pulse digitally delayed by one CLOCK cycle connected to the first phase detector input 511 with the Integer PWM Pulse delayed by the full delay line 500 and connected to the phase detector second input 512. A phase error between the two delayed versions of the Integer PWM Pulse will cause the bias control unit 520 to adjust the delays of the respective stages of the delay line 500 to correct for the phase error. Because this bias voltage is coupled to each of the inverter pairs of the delay stages 500-1, 500-2, . . . , 500-N of the tapped delay line 500, the amount of delay imparted by each delay stage will be appropriately compensated, so that the selected fractional CLOCK cycle adjustment of the Integer PWM Pulse at the output of OR gate 540 will be maintained effectively independent of processing variations and operational parameters.
Although the PLL and ‘pseudo PLL’ based tapped delay line schemes of FIGS. 4 and 5, respectively, provide a substantial improvement over the non-PLL configured delay line architecture of FIG. 2, they are still essentially analog approaches in that the delay elements need to be designed to approximate a specific fraction of the CLOCK signal cycle. Moreover, they are not perfectly ‘portable’ among different semiconductor fabrication plants, whose manufacturing parameters can be expected to vary from facility to facility, and therefore require adjustment of the delay line layouts.